Low latency speculative error correction using simplified ML detector for 64Gbps wireline transceiver

Abstract

Wireline interconnect data-rates have been doubling consistently every 3–4 years due to increasing demand for higher connectivity speed in datacenters. With limited improvement of the electrical channels, MLSE has emerged as a key digital technique for boosting signal power in wireline links, at the price of increased latency and die area. This paper presents an ultra-low latency speculative error correction (SEC) engine embedded within the DFE. It uses a simplified ML detector to correct single-symbol errors before they propagate into a burst. Significant reduction of the trellis size is achieved by using soft information together with assumptions on the error distribution. The design was customized for an existing Gen6 PCIe PHY in 5nm CMOS technology. Simulated and measured SNR gain exhibits comparable performance at a fraction of the latency and area of full MLSE.