Automotive and wireline PHYs
Leadership in 10GBASE-T1 automotive Ethernet, PCIe/CXL, long-reach wireline links, and optical interface DSPs.
Ehud Nir — Engineering Leadership in Advanced Connectivity ICs
ASIC and Chiplet R&D technical leader for automotive networking and wireline/optical connectivity products.
General Manager & Sr. Director of Engineering, Ethernovia Canada Inc.
Previously at: Cadence · Rambus · Huawei · IBM · STMicroelectronics
- 25+ years DSP, high-speed interfaces, and custom digital design experience
- Global teams 15+ years of Leadership across North America, Israel, India, and China
- 16–5nm advanced-node tapeout every ~18 months
- 2025 DesignCon Best Paper recognition
From DSP architecture to production-ready SoCs
Ehud Nir is a senior ASIC engineering leader focused on automotive networking, PHY SoCs and high-speed DSP innovation. He is Sr. Director of ASIC Engineering and General Manager at Ethernovia Canada, where he leads a global team developing 10GBASE-T1 automotive Ethernet SoCs and drives architecture, specifications, quality, compliance, power, safety, and production readiness.
His career combines leadership and hands-on execution across Ethernovia, Cadence, Rambus/AnalogX, Huawei, IBM, and STMicroelectronics. He has led end-to-end ASIC development, covering DSP architecture, AFE integration, microarchitecture, RTL, verification, backend and STA, firmware, and lab validation, while building and scaling international R&D teams across North America, Israel, India, and China.
His work includes advanced-technology Ethernet, PCIe, and multi-protocol SERDES PHY ASIC and IP development, from architecture to production silicon. He has authored and co-authored papers and patents, including a DesignCon25 Best Paper Award. He holds B.Sc. and M.Sc. degrees in Electrical and Electronics Engineering from Tel Aviv University.
Where the work stands out
End-to-end ASIC execution
Scope covering architecture, RTL, verification, synthesis, STA, backend integration, firmware, and lab bring-up.
Global engineering leadership
Built and led distributed R&D teams while setting work plans, mentoring engineers, and aligning technology with product requirements.
Papers
Low latency speculative error correction using simplified ML detector for 64Gbps wireline transceiver
Ehud Nir, Mansi Mehrotra, Amin Karami, Chris Holdenried, Robert Wang
8.8 A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver
James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto
Patents
Signaling compression and decompression associated with a partially unrolled decision feedback equalizer (DFE)
Patent #12294474 — Issued May 6, 2025
Amplitude optimized reflection canceller in parallel channel equalizers
Patent #12237951 — Issued February 25, 2025
System and method for low jitter phase-lock loop based frequency synthesizer
Patent #11245407 — Issued February 8, 2022
SerDes with jitter injection self stress mechanism
Patent #10693589 — Issued June 23, 2020
Systems and methods for memory device precharging
Patent #8472271 — Issued June 25, 2013
External links