STA in multi-GHz custom circuits made easy with NanoTime

Abstract

High speed digital blocks in mixed signal IPs are designed using full custom flow, to maximize the performance while meeting the required area and power constraints. On the other hand, industry trends such as IP quality, predictability and time to market suggest employing EDA tools wherever possible in the design. This paper will address the challenges in the STA domain, by examining NanoTime transistor level static timing flow, executed on a CMOS levels 30GSPS serializer. Although the employed latch topology is not automatically recognized by NanoTime, using manual latch marking and custom timing checks, 100% of the IN2REG and REG2REG timing arcs can be covered. NanoTime capabilities such as parasitic back annotation and POCV are discussed. Tool accuracy is compared against automatically generated spice deck and original schematic dynamic simulation. The work is summarized with a list of conclusions and follow-up work.